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overview the LC78630E is a cd-da signal-processing lsi for use in video cd player systems. the LC78630E incorporates signal-processing circuits for demodulating and de- interleaving the efm signal from the optical pickup, error detection and correction, and digital filtering. it also includes a 1-bit d/a converter and executes commands sent from a system control microprocessor. features ? built-in pll for efm signal synchronization (a hybrid analog-digital pll that supports 4 playback) ? built-in pll for variable pitch playback (13%) ? 18kb ram on chip ? error detection and correction (corrects two errors in c1 and four errors in c2) ? frame jitter margin: 8 frames ? frame synchronization signal detection, protection, and insertion ? dual interpolation adopted in the interpolation circuit. ? efm data demodulation ? subcode demodulation ? zero-cross muting adopted ? servo command interface ? 2fs digital filter ? digital de-emphasis ? built-in independent left- and right-channel digital attenuators (239 attenuation steps) ? left/right swap function ? built-in 1-bit d/a converter (third-order ? noise shaper, pwm output) ? built-in digital output circuit ? clv servo ? arbitrary track jumping (of up to 255 tracks) ? variable sled voltage (four levels) ? built-in oscillator circuit using an external 16.9344 mhz or 33.8688 mhz (for 4 playback) element ? supply voltage: 3.6 to 5.5 v (4.5 to 5.5 v for 4 playback mode) ? six extended i/o ports and 2 extended output ports package dimensions unit: mm 3174-qfp80e cmos lsi ordering number : en 5121b 83097ha (ot)/d3095ha (ot)/60595ha (ot) no. 5121-1/33 sanyo: qip80e [LC78630E] sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan compact disk player dsp LC78630E
equivalent circuit block diagram no. 5121- 2 /33 LC78630E
pin assignment absolute maximum ratings at ta = 25 c, v ss = 0 v allowable operating ranges at ta = 25 c, v ss = 0 v no. 5121- 3 /33 LC78630E parameter symbol conditions ratings unit maximum supply voltage v dd max C0.3 to +7.0 v input voltage v in C0.3 to v dd + 0.3 v output voltage v out C0.3 to v dd + 0.3 v allowable power dissipation pd max 470 mw operating temperature topr C30 to +75 c storage temperature tstg C40 to +125 c parameter symbol conditions min typ max unit v dd 1 v dd , av dd , xv dd , lv dd , rv dd 3.6 5.0 5.5 v supply voltage v dd 2 v dd , av dd , xv dd , lv dd , rv dd : for 4 playback or 4.5 5.0 5.5 v variable-pitch playback test1 to test5, tai, hfl, tes, p0/dfck, p1/dfin, input high-level voltage v ih 1 p2, p3/dflr, p4, p5, sbck, rwc, coin, cqck, 0.7 v dd v dd v res, cs, x in , defi v ih 2 efmi 0.6 v dd v dd v test1 to test5, tai, hfl, tes, p0/dfck, p1/dfin, input low-level voltage v il 1 p2, p3/dflr, p4, p5, sbck, rwc, coin, cqck, 0 0.3 v dd v res, cs, x in , defi v il 2 efmi 0 0.4 v dd v data setup time t su coin, rwc: figures 1 and 4 400 ns t prs rwc: figure 4 100 ns data hold time t hd coin, rwc: figures 1 and 4 400 ns continued on next page.
continued from preceding page. note: due to the structure of this ic, the identical voltage must be applied to all power-supply pins. electrical characteristics at ta = 25 c, v dd = 5 v, v ss = 0 v no. 5121- 4 /33 LC78630E parameter symbol conditions min typ max unit high-level clock pulse width t wh sbck, cqck: figures 1, 2, 3, and 4 400 ns low-level clock pulse width t wl sbck, cqck: figures 1, 2, 3, and 4 400 ns data read access time t rac sqout, pw: figures 2, 3, and 4 0 400 ns command transfer time t rwc rwc: figures 1 and 4 1000 ns subcode q read enable time t sqe wrq: figure 2, with no rwc signal 11.2 ms subcode read cycle t sc sfsy: figure 3 136 s subcode read enable t se sfsy: figure 3 400 ns port output delay time t pd cont1, cont2, p0 to p5: figure 5 1200 ns input level v ei efmi 1.0 vp-p v xi x in : capacitance coupled input 1.0 vp-p parameter symbol conditions min typ max unit current drain i dd 30 ma i ih 1 efmi, hfl, tes, sbck, rwc, coin, cqck, res, 5 a input high-level current defi: v in = 5 v i ih 2 tai, test1 to test5, cs: v in = 5 v 25 75 a input low-level current i il tai, efmi, hfl, tes, sbck, rwc, coin, cqck, res, C5 a test1 to test5, cs, defi: v in = 0 v v oh 1 efmo, clv + , clv C , v/p, pck, fseq, toff, tgl, 4 v thld, jp + , jp C , emph, eflg, fsx: i oh = C1 ma mutel, muter, lrcko, dflro, dacko, p0/dfck, v oh 2 p1/dfin, p2, p3/dflr, p4, p5, lrsy, ck2, romxa, 4 v output high-level voltage c2f, sbsy, pw, sfsy, wrq, sqout, 16m, 4.2m, cont1, cont2: i oh = C0.5 ma v oh 3 vpdo: i oh = C1 ma 4.5 v v oh 4 dout: i oh = C12 ma 4.5 v v oh 5 lchp, rchp, lchn, rchn: i oh = C1 ma 3.0 4.5 v v ol 1 efmo, clv + , clv C , v/p, pck, fseq, toff, tgl, 1 v thld, jp + , jp C , emph, eflg, fsx: i ol = 1 ma mutel, muter, lrcko, dflro, dacko, p0/dfck, v ol 2 p1/dfin, p2, p3/dflr, p4, p5, lrsy, ck2, romxa, 0.4 v output low-level voltage c2f, sbsy, pw, sfsy, wrq, sqout, 16m, 4.2m, cont1, cont2: i ol = 2 ma v ol 3 vpdo: i ol = 1 ma 0.5 v v ol 4 dout: i ol = 12 ma 0.5 v v ol 5 lchp, rchp, lchn, rchn: i ol = 1 ma 0.5 2.0 v i off 1 pdo1, pdo2, vpdo, p0/dfck, p1/dfin, 5 a output off leakage current p2, p3/dflr, p4, p5: v out = 5 v i off 2 pdo1, pdo2, vpdo, p0/dfck, p1/dfin, C5 a p2, p3/dflr, p4, p5: v out = 0 v charge pump output current i pdoh pdo1, pdo2: r iset = 68 k C96 C80 C64 a i pdol pdo1, pdo2: r iset = 68 k 64 80 96 a v sld 1 1.0 1.25 1.5 v sled output voltage v sld 2 2.25 2.5 2.75 v v sld 3 3.5 3.75 4.0 v v sld 4 4.75 v
d/a converter analog characteristics at ta = 25 c, v dd = 5 v, v ss = 0 v note: measured in normal-speed playback mode in a sanyo 1-bit d/a converter block reference circuit, with the digital attenuator set to ee`p (hexadecimal). no. 5121- 5 /33 LC78630E parameter symbol conditions min typ max unit total harmonic distortion thd + n lchp, lchn, rchp, rchn; 1 khz: 0 db input, 0.006 % using a 20-khz low-pass filter (ad725d built in) dynamic range dr lchp, lchn, rchp, rchn; 1 khz: C60 db input, using 90 db the 20-khz low-pass filter (a filter (ad725d built in)) signal-to-noise ratio s/n lchp, lchn, rchp, rchn; 1 khz: 0 db input, using 98 100 db the 20-khz low-pass filter (a filter (ad725d built in)) crosstalk ct lchp, lchn, rchp, rchn; 1 khz: 0 db input, 96 98 db using a 20-khz low-pass filter (ad725d built in)
no. 5121- 6 /33 LC78630E
one-bit d/a converter output block reference circuit no. 5121- 7 /33 LC78630E
pin functions no. 5121- 8 /33 LC78630E pin no. symbol i/o function 1 vpdo o variable pitch pll charge pump output. must be left open if unused. 2 pdo2 o double-speed and quad-speed mode playback pll charge pump output. must be left open if unused. 3 pdo1 o normal-speed mode playback pll charge pump output 4 av ss analog system ground. normally 0 v. 5 fr built-in vco frequency range setting resistor connection 6 av dd analog system power supply. 7 iset pdo1 and pdo2 output current setting resistor connection 8 tai i test input. a pull-down resistor is built in. 9 efmo o efm signal output 10 v ss digital system ground. normally 0 v. 11 efmi i efm signal input 12 test1 i test input. a pull-down resistor is built in. 13 clv + o spindle servo control output. clv + outputs a high level for acceleration, and clv C outputs a high level for 14 clv C o deceleration. 15 v/p o rough servo/phase control automatic switching monitor output. a high-level output indicates rough servo, and a low-level output indicates phase control. 16 test2 i test input. a pull-down resistor is built in. 17 test3 i test input. a pull-down resistor is built in. 18 p4 i/o i/o port 19 hfl i track detection signal input. this is a schmitt input. 20 tes i tracking error signal input. this is a schmitt input. 21 pck o efm data playback bit clock monitor. outputs 4.3218 mhz when the phase is locked in normal-speed mode playback. 22 fseq o synchronization signal detection output. outputs a high level when the synchronization signal detected from the efm signal matches the internally generated synchronization signal. 23 toff o tracking off output 24 tgl o tracking gain switching output. increase the gain when this pin outputs a low level. 25 thld o tracking hold output. 26 test4 i test input. a pull-down resistor is built in. 27 v dd digital system power supply. 28 jp + o track jump output. jp + outputs a high level both for acceleration during outward direction jumps and for deceleration during inward direction jumps. jp C outputs a high level both for acceleration during inward direction 29 jp C o jumps and for deceleration during outward direction jumps. 30 sld + o sled output. this pin can be set to 1 of 4 levels by commands sent from the system control microprocessor. 31 sld C o 32 emph o de-emphasis monitor. a high level indicates that a disk requiring de-emphasis is being played. 33 p5 i/o i/o port 34 lrcko o lr clock output 35 dflro o digital filter outputs lr data output. the digital filter can be turned off with the dfoff command. 36 dacko o bit clock output 37 cont1 o output port 38 p0/dfck i/o i/o port or digital filter bit clock input 39 p1/dfin i/o i/o port or digital filter data input 40 p2 i/o i/o port. used as the de-emphasis filter on/off switching pin in antishock mode. the de-emphasis filter is turned on when this pin is high. 41 p3/dflr i/o i/o port output or digital filter lr clock input (when anti-shock mode) 42 lrsy o lr clock output 43 ck2 o bit clock output. the polarity can be inverted with the ck2con command. 44 romxa o romxa pins interpolated data output. data that has not been interpolated can be output by issuing the romxa command. 45 c2f o c2 flag output 46 mutel o left channel mute output 47 lv dd left channel power supply. 48 lchp o one-bit d/a left channel p output 49 lchn o converter pins left channel n output 50 lv ss left channel ground. normally 0 v.
continued from preceding page. no. 5121- 9 /33 LC78630E pin no. symbol i/o function 51 xv ss crystal oscillator ground. normally 0 v. 52 x out o 16.9344 mhz crystal oscillator connections. use a 33.8688 mhz crystal oscillator for quad-speed playback. 53 x in i 54 xv dd crystal oscillator power supply. 55 rv ss right channel ground. normally 0 v. 56 rchn o one-bit d/a right channel n output 57 rchp o converter pins right channel p output 58 rv dd right channel power supply. 59 muter o right channel mute output 60 sbsy o subcode block synchronization signal output 61 eflg o c1 and c2 error correction state monitor 62 pw o subcode p, q, r, s, t, u, v, and w output 63 sfsy o subcode frame synchronization signal output. falls when the subcode output goes to the standby state. 64 sbck i subcode readout clock input. this is a schmitt input. 65 dout o digital output 66 fsx o outputs a 7.35 khz synchronization signal generated by dividing the crystal oscillator frequency. 67 wrq o subcode q output standby output 68 rwc i read/write control input 69 sqout o subcode q output 70 coin i input for commands from the control microprocessor 71 cqck i command input acquisition clock. also used as the sqout subcode readout clock input. this is a schmitt input. 72 res i chip reset input. this pin must be set low temporarily when power is first applied. 73 testf o test output 74 cont2 o output port 75 16m o 16.9344 mhz output. 33.8688 mhz output in 4 playback mode 76 4.2m o 4.2336 mhz output 77 test5 i test input. a pull-down resistor is built in. 78 cs i chip select input. a pull-down resistor is built in. must be connected to ground if unused. 79 defi i defect detection signal input. must be connected to ground if unused. 80 vcoc i variable pitch vco control input. must be connected to ground if unused.
cd d/a converter block diagram 1. hf signal input circuit; pin 11: efmi, pin 9: efmo, pin 79: defi, pin 13: clv + when an hf signal is input to efmi, the circuit slices it at an optimal level to produce an efm (nrz) signal. to deal with defects, if the defi pin (pin 79) goes high, the slice level control output (efmo, pin 9) goes to the high-impedance state and the slice level is held. however, this function only operates when clv is in phase control mode, i.e., when the v/ p pin (pin 15) is low. this function can be formed by combining with the def pin on the la9230/40 series lsi. note: if the efmi and clv + lines are placed too close together, spurious radiation (induced noise) can degrade the error rate. therefore we recommend laying a ground or v dd shielding line between these lines. 2. pll clock reproduction circuit; pin 2: pdo2, pin 3: pdo1, pin 5: fr, pin 7: iset, pin 21: pck this block includes a vco circuit, and a pll circuit is formed using external resistors and capacitors. iset is the charge pump reference current, pdo1 and pdo2 are the loop filters, and fr determines the vco frequency range. (reference values) r1 = 68 k , c1 = 0.1 f r2 = 680 , c2 = 0.1 f r3 = 680 , c3 = 0.047 f r4 = 1.2 k 3. synchronization detection monitor; pin 22: fseq this pin outputs a high level when the frame sync (positive synchronizing signal), which is read by pck from the efm signal, and the timing (the inserted synchronizing signal), which is generated by a counter, agree. thus this pin functions as a synchronization monitor. note that it is held high during one frame. no. 5121- 10 /33 LC78630E
4. command input an external controller can execute LC78630E instructions by setting rwc high and inputting commands to coin in synchronization with the cqck clock. commands are executed on the fall of the rwc signal. ? single-byte commands ? two-byte commands ? command noise reduction this command can reduce the noise on the cqck clock signal. while this is effective for noise pulses under 500 ns, the use of this function requires that the cqck timings t wl , t wh , and t su (see figure 1 and 2) be set to 1 s or longer. 5. clv servo circuit ? clv servo circuit; pin 13: clv + , pin 14: clv C , pin 15: v/p the clv + signal causes the disc to accelerate in the forward direction, and clv C causes the disc to decelerate. the microcontroller can select one of four modes: accelerate, decelerate, clv, and stop. the table below lists the states of the clv + and clv C pins in each of these modes. note: the clv servo control commands only set the toff pin low during clv mode. that pin will be at the high level at all other times. thus controlling the toff pin with microcontroller commands is only possible in clv mode. no. 5121- 11 /33 LC78630E code command res = low $ef command input noise reduction mode $ee clear the above mode m code command res = low $04 disc motor start (accelerate) $05 disc motor clv (clv) $06 disc motor brake (decelerate) $07 disc motor stop (stop) m mode clv + clv C accelerate high low decelerate low high clv pulse output pulse output stop low low
? clv mode in clv mode, the system detects the disc speed from the hf signal and holds the disc at the prescribed linear speed using multiple control methods switched by changing the dsp internal mode. the pwm frequency is 7.35 khz. the v/p pin outputs a high level when the system is in rough servo mode and a low level when it is in phase control mode. ? rough servo gain switching the clv control gain in rough servo mode can be reduced by 8.5 db from the 12-cm disc setting for 8-cm discs. ? phase control gain switching the phase control gain can be switched by switching the value of the divisor in the dividers in the stage preceding the phase comparator. ? internal brake modes no. 5121- 12 /33 LC78630E internal mode clv + clv C v/p rough servo (velocity too low) high low high rough servo (velocity too high) low high high phase control (pck locked) pwm pwm low code command res = low $a8 8- cm disc loaded $a9 12- cm disc loaded m code command res = low $b1 clv phase comparator divisor: 1/2 $b2 clv phase comparator divisor: 1/4 $b3 clv phase comparator divisor: 1/8 $b0 no clv phase comparator divisor used m code command res = low $c5 internal brake on $c4 internal brake off m $a3 internal brake cont $cb internal brake continuous mode $ca reset continuous mode m $cd ton mode during internal braking $cc reset ton mode m
inputting the internal brake on command ($c5) sets the system to internal braking mode. in this mode, executing a brake command ($06) allows the disc deceleration state to be monitored from the wrq pin. in this mode the system counts the density of the efm signal during one frame to determine the disk deceleration state and drops clv C to low when the efm signal falls to 4 or lower. at this point, it sets the wrq signal high as a braking complete monitor. when the microcontroller detects a high level on the wrq signal, it should issue a stop command to completely stop the disc. in internal braking continuous mode ($cb), the lsi continues the braking operation by holding clv C high even after the wrq braking done monitor signal has been set high. note that there are cases where, to compensate for incorrect braking state recognition due to noise in the efm signal, the efm signal count should be changed from 4 to 8 using the internal brake control command ($a3). in ton mode during internal braking ($cd), the toff signal is set low during internal braking operation. we recommend using this mode, since it is effective at preventing incorrect detection at the disk mirror surface. note: 1. if focus is lost during the execution of an internal braking command, the pickup must be refocussed and the internal braking command must be input once again. 2. since incorrect judgments are possible due to the efm signal reproduction state (due damaged disks, access in progress, and other problems), we recommend using a microcontroller in conjunction with this lsi. 6. track jump ? track jump circuit; pin 19: hfl, pin 20: tes, pin 23: toff, pin 24: tgl, pin 25: thld, pin 28: jp + , pin 29: jp C the LC78630E supports the two track count modes listed below. the old track count function uses the tes signal directly as the internal track counter clock. to reduce counting errors resulting from noise on the rising and falling edges of the tes signal, the new track count function prevents noise induced errors by using the combination of the tes and hfl signals, and implements a more reliable track count function. however, dirt and scratches on the disk can result in hfl signal dropouts that may result in missing track count pulses. thus care is required when using this function. the new track jump mode applies a window to the tes and hfl signals. the LC78630E provides two widths for this window. tes wd wide ..................... the maximum input frequency for tes and hfl is 60 khz. tes wd narw ................... the maximum input frequency for tes and hfl is 120 khz. no. 5121- 13 /33 LC78630E code command res = low $22 new track count (using the tes/hfl combination) l l $23 old track count (directly counts the tes signal) code command res = low $ba tes wd wide l l $bb tes wd narw
? tj commands when the LC78630E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). the passage of the braking period (period c) completes the specified jump. during the braking period, the LC78630E detects the beam slip direction from the tes and hfl inputs. toff is used to cut the components in the tes signal that aggravate slip. the jump destination track is captured by increasing the servo gain with tgl. in thld period toff output mode the toff signal is held high during the period when thld is high. note: of the modes related to disk motor control, the toff pin only goes low in clv mode, and will be high during start, stop, and brake operations. note that the toff pin can be turned on and off independently by microprocessor issued commands. however, this function is only valid when disk motor control is in clv mode. no. 5121- 14 /33 LC78630E code command res = low $a0 old track jump l l $a1 new track jump $11 1 track jump in #1 $12 1 track jump in #2 $31 1 track jump in #3 $52 1 track jump in #4 $10 2 track jump in $13 4 track jump in $14 16 track jump in $30 32 track jump in $15 64 track jump in $17 128 track jump in $19 1 track jump out #1 $1a 1 track jump out #2 $39 1 track jump out #3 $5a 1 track jump out #4 $18 2 track jump out $1b 4 track jump out $1c 16 track jump out $38 32 track jump out $1d 64 track jump out $1f 128 track jump out $16 256 track check $0f toff $8f ton l l $8c track jump brake $21 thld period toff output mode
? track jump modes the table lists the relationships between acceleration pulses (the a period), deceleration pulses (the b period), and the braking period (the c period). note: 1. as indicated in the table, actuator signals are not output during the 256 track check function. this is a mode in which the tes signal is counted in the tracking loop off state. therefore, feed motor forwarding is required. 2. the servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. a new track jump command cannot be input during a track jump operation. 4. the 1 track jump #3 and 2 track jump modes do not have a braking period (the c period). since brake mode must be generated by a n external circuit, care is required when using this mode. when the LC78630E is used in combination with a la9230/40 series lsi, since the thld signal is generated by the la9230/40 serie s lsi, the thld pin (pin 25) will be unused, i.e., have no connection. no. 5121- 15 /33 LC78630E old track jump mode new track jump mode command a b c a b c 1 track jump in (out) #1 233 s 233 s 60 ms 233 s 233 s 60 ms 1 track jump in (out) #2 0.5 track 233 s 60 ms 0.5 track same period as a 60 ms jump period jump period 1 track jump in (out) #3 0.5 track 233 s this period does 0.5 track same period as a this period does jump period not exist. jump period not exist. 0.5 track 60 ms; toff is 0.5 track 60 ms; toff is 1 track jump in (out) #4 jump period 233 s low during jump period same period as a low during the c period. the c period. 2 track jump in (out) none none none 1 track same period as a this period does jump period not exist. 4 track jump in (out) 2 track 466 s 60 ms 2 track same period as a 60 ms jump period jump period 16 track jump in (out) 9 track 7 track 60 ms 9 track same period as a 60 ms jump period jump period jump period 32 track jump in (out) 18 track 14 track 60 ms 18 track 14 track 60 ms jump period jump period jump period jump period 64 track jump in (out) 36 track 28 track 60 ms 36 track 28 track 60 ms jump period jump period jump period jump period 128 track jump in (out) 72 track 56 track 60 ms 72 track 56 track 60 ms jump period jump period jump period jump period toff goes high during the period toff goes high during the period 256 track check when 256 tracks are passed over. 60 ms when 256 tracks are passed over. 60 ms the a and b pulses are not output. the a and b pulses are not output. track jump brake there are no a or b periods. 60ms there are no a and b periods. 60 ms
5. tracking brake the chart shows the relationships between the tes, hfl, and toff signals during the track jump c period. the toff signal is ext racted from the hfl signal by tes signal edges. when the hfl signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. thus braking is applied based on the toff signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region. ? arbitrary track jump command the LC78630E performs arbitrary track jump operations specified by an arbitrary binary value in the range 16 to 255 and an arbitrary track jump in or out command. however, to improve pickup set ability, the LC78630E monitors the tes signal half-period, and when it detects a pickup speed of 0, it terminates the track jump operation. use the old fixed track jump (1tj and 4tj) commands to cross 15 or fewer tracks. acceleration period (a) this period is over when 8/16, 9/16, or 10/16 times the number of tracks to be jumped have been counted. the mode setting command is used to select 8/16, 9/16, or 10/16. the result of this calculation (e.g. (n 8)/16, where n is the number of tracks to be jumped) is rounded to an integer. deceleration period (b) the LC78630E monitors the tes signal half-period, and terminates the operation at the point the set time has passed. the mode setting command is used to set the time. as a b period protection function, the LC78630E terminates the operation if at most the time required for the a period elapses. no. 5121- 16 /33 LC78630E code command res = low $77 arbitrary track jump in $7f arbitrary track jump out $48 arbitrary track jump mode data byte + $77 ($7f) arbitrary track jump in ( or out)
braking period (c) this period ends when the wrq signal rises, i.e. at the point subcodes can be read. if wrq does not go high, the period is terminated if 60 ms elapse. note: since sled forwarding is not performed, a sled forwarding operation is necessary for large track jumps. arbitrary track jump mode is initialized by the following 2-byte command. the lower 6 bits of the data byte set the track jump acceleration period (a) and the track jump deceleration period (b). the period a is calculated from the given n and rounded to an integer. the LC78630E monitors the tes half period and terminates the b period if a period longer than the set period elapses. the tes half period for b period termination is (123 d3) + (62 d2) + (32 d1) + (17 d0) s note: * the maximum value (306 s) is set when [d3 d2 d1 d0] = [0 0 0 0]. ? track check mode the LC78630E will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 8 to 254 and either a track check in or a track check out 2-byte command. no. 5121- 17 /33 LC78630E data byte + $48 arbitrary track jump mode set command d5 d4 track jump acceleration period 0 0 (8/16) n tracks 0 1 (9/16) n tracks 1 0 (10/16) n tracks d3 d2 d1 d0 tes half period 0 0 0 0 306 s * 0 0 0 1 17 s 0 0 1 0 32 s 0 1 0 0 62 s 1 0 0 0 123 s code command res = low $f0 track check in $f8 track check out $ff track check clear m
note: 1. during a track check operation the toff pin goes high and the tracking loop is turned off. therefore, feed motor forwarding is required. 2. when a track check in/out command is issued the function of the wrq signal switches from the normal mode subcode q standby moni tor function to the track check monitor function. this signal goes high when the track count is half completed, and goes low when t he count finishes. the control microprocessor should monitor this signal for a low level to determine when the track check completes. 3. if a track check clear command ($ff) is not issued, the track check operation will repeat. this can be used. for example, to sk ip over 20,000 tracks, issue a track check 199 code once, and then count the wrq signal 100 times. this will count 20,000 tracks. 4. after performing a track check operation, use the tj brake command to lock the pickup onto the track. 7. sled output; pin 30: sld + , pin 31: sld C the sled + and sled C outputs can be set independently to one of four levels using this 2-byte command. neither sled + nor sled C are output after a reset. sled + and sled C output is selected by the most significant bit in the data byte. the sled output level is set by the lower 3 bits. when sled + is set, sled C is automatically set to v ss (sled off). the inverse is also true. 8. error flag output; pin 61: eflg, pin 66: fsx no. 5121- 18 /33 LC78630E data byte + $b8 sled output setting code command res = low $b8 sled set d7 output pin 0 sled + 1 sled C d2 d1 d0 output level 0 0 0 v ss (sled off) 0 0 1 0.25 v dd 0 1 0 0.5 v dd 0 1 1 0.75 v dd 1 0 0 v dd
fsx is a 7.35 khz frame synchronization signal generated by dividing the crystal clock. the error correction state for each frame is output from eflg. eflg indicates the c1 correction state while fsx is high and the c2 correction state while fsx is low. the playback ok/ng state can be easily determined from the number of high levels that appear here. note: the fsx polarity is opposite in the lc78620 and lc7860 series lsis. 9. subcode p, q, and r to w output circuit; pin 62: pw, pin 60: sbsy, pin 63: sfsy, pin 64: sbck pw is the subcode signal output pin, and all the codes, p, q, and r to w can be read out by sending eight clocks to the sbck pin within 136 s after the fall of sfsy. the signal that appears on the pw pin changes on the rising edge of sbck. if a clock is not applied to sbck, the p code will be output from pw. sfsy is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (p to w). subcode data p is output on the fall of this signal. sbsy is a signal output for each subcode block. this signal goes high for the s0 and s1 synchronizing signals. the fall of this signal indicates the end of the subcode synchronizing signals and the start of the data in the subcode block. (eiaj format) 10. subcode q output circuit; pin 67: wrq, pin 68: rwc, pin 69: sqout, pin 71: cqck , pin 78: cs subcode q can be read from the sqout pin by applying a clock to the cqck pin. of the eight bits in the subcode, the q signal is used for song (track) access and display. the wrq will be high only if the data passed the crc error check and the subcode q format internal address is 1*. the control microprocessor can read out data from sqout in the order shown below by detecting this high level and applying cqck. when cqck is applied the dsp disables register update internally. the microprocessor should give update permission by setting rwc high briefly after reading has completed. wrq will fall to low at this time. since the wrq high period is 11.2 ms, cqck must be applied during the high period. note that data is read out in an lsb first format. note: if rwc is set high by command while wrq is high, wrq will return to low and the sqout data will be invalid. note: * this state will be ignored if an address free command is sent. no. 5121- 19 /33 LC78630E code command res = low $09 address free $89 address 1 m
note: 1. normally, the wrq pin indicates the subcode q standby state. however, it is used for a different monitoring purpose in track ch eck mode and during internal braking. (see the items on track checking and internal braking for details.) 2. the LC78630E becomes active when the cs pin is low, and subcode q data is output from the sqout pin. when the cs pin is high, t he sqout pin goes to the high-impedance state. the atime priority command allows the sqout output to read from atime. in this mode, data is output in a ring sequence in the order: amin, asec, aframe, cont, adr, etc. 11. mute control circuit muting of C db can be applied by issuing the command shown above. the adoption of a zero-cross muting algorithm means that noise is minimal. a zero crossing is recognized when the sign bit of the code changes state. no. 5121- 20 /33 LC78630E code command res = low $4b atime priority on $4a atime priority off m code command res = low $01 mute 0 db $03 mute C db m
12. interpolation circuit outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. to minimize this noise, the LC78630E replaces incorrect data with linearly interpolated data based on the correct data on both sides of the incorrect data. if incorrect data continues for two or more consecutive values, the LC78630E holds the previous correct data value and then applies average value interpolation to the previous incorrect value of the next correct data value to calculate the value that precedes the next correct value. 13. bilingual function ? following a reset or when a stereo ($28) command has been issued, the left and right channel data is output to the left and right channels respectively. ? when an lch set ($29) command is issued, the left and right channels both output the left channel data. ? when an rch set ($2a) command is issued, the left and right channels both output the right channel data. 14. de-emphasis; pin 32: emph the pre-emphasis on/off bit in the subcode q control information is output from the emph pin. when this pin is high, the LC78630E internal de-emphasis circuit operates and the digital filter and the d/a converter output de- emphasized data. 15. digital attenuator attenuation can be applied to the left and right channel audio data independently by issuing two-byte commands. alternatively, both channels can be attenuated at the same time using the $81 command. no. 5121- 21 /33 LC78630E code command res = low $28 sto cont m $29 lch cont $2a rch cont code command res = low $81 l ch , r ch att set $82 lch att set $83 rch att set
? attenuation settings the attenuation is set by the attenuation data in the first byte and the command in the byte that follows. the data value can be in the range $00 to $ee (0 to 238). audio output = 20 log [db] since the att data is set to 0 (a muting of C ) by a reset, to output the audio signal, the control microprocessor must issue, for example, a $ee + $81 command, thus setting both the left and right channels to C0.63 db. note: to prevent noise due to arithmetic overflow in the 1-bit d/a converter, data values of $ef (att data = 239) or larger are not allowed. ? mute output; pin 46: mutel, pin 59: muter these pins output a high level when the attenuator coefficient is set to $00 and the data in each channel has been zero continuously for a certain period. if data input occurs once again, these pins go low immediately. 16. digital filter outputs; pin 34: lrcko, pin 35: dflro, pin 36: dacko dflro outputs 2 oversampled data for use with an external d/a converter msb first in synchronization with the falling edge of dacko. these pins are provided so that an external d/a converter can be used if desired. 17. swap; pin 48: lchp, pin 49: lchn, pin 56: rchn, pin 57: rchp the swap command swaps the d/a converter left and right channel outputs. 18. one-bit d/a converter ? the LC78630E pwm block outputs one data value in the range C3 to +3 once every 64fs period. to reduce carrier noise, this block adopts an output format in which the output is adjusted so that the pwm output level does not invert between consecutive data items. also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. this block outputs a positive phase signal to the lchp (rchp) pin and a negative phase signal to the lchn (rchn) pin. high-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. the LC78630E includes built-in radiation suppression resistors (1 k ) in each of the lchp/n and rchp/n pins. att data 256 no. 5121- 22 /33 LC78630E code command res = low $85 swap on $84 swap off l l
? pwm output format ? pwm output example 19. cd-rom outputs; pin 42: lrsy, pin 43: ck2, pin 44: romxa, pin 45: c2f although the LC78630E is initially set up to output audio data msb first from the romxa pin in synchronization with ck2, it can be switched to output cd-rom data by issuing a cd-rom xa command. since this data has not been processed by the interpolation, previous value hold, muting, and other digital circuits, it is appropriate for input to a cd-rom decoder lsi. ck2 is a 2.1168 mhz clock, and data is output on the ck2 falling edge. however, this clock polarity can be inverted by issuing a ck2 polarity inversion command. c2f is the flag information for the data in 8-bit units. note that the cd-rom xa reset command has the same function as the cont1 pin (pin 37). no. 5121- 23 /33 LC78630E code command res = low $88 cd rom xa $8b cont and cd-rom xa reset m $c9 ck2 polarity inversion
20. digital output circuit; pin 65: dout this is an output pin for use with a digital audio interface. data is output in the eiaj format. this signal has been processed by the interpolation and muting circuits. this pin has a built-in driver circuit and can directly drive a transformer. ? the digital out pin can be locked at the low level by issuing a dout off command. ? the ubit information in the dout data can be locked at zero by issuing a ubit off command. ? the dout data can be switched to data to which interpolation and muting have not been applied by issuing a cd- rom xa command. 21. antishock support; pin 38: p0/dfck, pin 39: p1/dfin, pin 40: p2, pin 41: p3/dflr, pin 42: lrsy, pin 43: ck2, pin 44: romxa, pin 45: c2f antishock mode is a mode in which antishock processing is applied to data that has been output once. that data is returned and output once again as an audio playback signal. it is also possible to use only the audio playback block (the attenuator, digital filter, and d/a converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with the LC78630E clock. ? the signals from the romxa pin can be output to an antishock lsi (the sanyo lc89151) and re-input the signals output by the antishock lsi to the LC78630E p1/dfin pin. these signals are then processed by the attenuator, digital filters, and d/a converter circuits and output as audio signals. in this mode, the p2 pin switches the de- emphasis filter on and off. when p2 is high, the de-emphasis filter will be on. ? in antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock lsi, and the audio playback block (the attenuator, digital filter, and d/a converter circuits) must operate at normal speed. this means that the control microprocessor must issue both the antishock on command ($6c) as well as the df normal speed on command ($6f). no. 5121- 24 /33 LC78630E code command res = low $42 dout on m $43 dout off $40 ubit on m $41 ubit off code command res = low $6c anti-shock on $6b anti-shock off m $6f df normal speed on (only in antishock mode) $6e df normal speed off (only in antishock mode) m
22. general-purpose output ports; pin 37: cont1, pin 74: cont2 the cont1 and cont2 pins can be set to high or low by commands from the control microprocessor. note that the cont1 reset command also resets the cd-rom xa mode, and thus care is required when using this command. 23. general-purpose i/o ports; pin 38: p0/dfck, pin 39: p1/dfin, pin 40: p2, pin 41: p3/dflr, pin 18: p4, pin 33: p5 the LC78630E provide six i/o ports: pins p0 to p5. these pins all function as input pins after a reset. unused ports must be connected to ground or set to output mode. the port information can be read from the sqout pin in the order p0 to p5 in synchronization with cqck falling edges by issuing the port read command. note that data can be read out in the same manner when another command is issued. these ports can be set independently to be control output pins by the two-byte port i/o set command. ports are selected with the lower 6 bits of the data byte. dn = 1 ................. sets port pn to be an output pin. dn = 0 ................. sets port pn to be an input pin. n = 0 to 5 no. 5121- 25 /33 LC78630E code command res = low $0e cont1 set $8b cont1 and cd-rom xa reset m $4d cont2 set $4c cont2 reset m code command res = low $dd port read $db port i/o set $dc port output data byte + $db port i/o set
ports set to be output pins can be independently set to be either high or low by the port output two-byte command. the lower 6 bits of the data byte correspond to the ports. dn = 1 ................. a high level is output from pn, assuming it is set up for output. dn = 0 ................. a low level is output from pn, assuming it is set up for output. 24. variable pitch playback; pin 1: vpdo, pin 80 vcoc the LC78630E includes a variable pitch pll circuit, and the disk rotation rate and the romxa output data transfer rate can be varied by varying the clock used as the time base in 0.1% increments over a range of 13%. a variable pitch circuit is formed by connecting a variable pitch low-pass filter to the vpdo and vcoc pins. note: variable pitch playback is not supported at 4 speed. the amount of variation is set by the data byte value n (as a twos complement number) and the variable pitch data set two-byte command. no. 5121- 26 /33 LC78630E data byte + $dc port output data byte + $da variable pitch data set code command res = low $d9 variable pitch on $d8 variable pitch off m $da variable pitch data set amount of change = n/10 [%] (n = C128 to +127)
25. clock oscillator; pin 53: x in , pin 52: x out the clock that is used as the time base is generated by connecting a 16.9344 or 33.8688 mhz oscillator element between these pins. the osc off command turns off both the vco and crystal oscillators. double- or quad-speed playback can be specified by microprocessor command. ? use a 16.9344 mhz oscillator element if the application circuit implements a 2 -speed playback system. the system control microprocessor can then issue 2 -speed or normal-speed playback commands. ? use a 33.8688 mhz oscillator element if the application circuit implements a 4 -speed playback system. the system control microprocessor can then issue 4 -speed, 2 -speed, or normal-speed playback commands. 26. 16m and 4.2m pins; pin 75: 16m, pin 76: 4.2m if a 16.9344 mhz oscillator element is used, the 16m pin will output a 16.9344 mhz signal from a buffer circuit in 2 -speed and normal-speed playback modes. if a 33.8688 mhz oscillator element is used, the 16m pin will output a 33.8688 mhz signal from a buffer circuit in 4 -speed playback mode. the 4.2m pin functions as the la9230/la9240 series system clocks and always outputs a 4.2336 mhz signal. in oscillator off mode, both of these pins are held either high or low. 27. reset circuit: pin 72: res this pin must be pulled low temporarily and then set high after power is first applied. this sets the muting to C db and the disc motor to stopped. setting the res pin low directly sets the states enclosed in boxes. no. 5121- 27 /33 LC78630E code command res = low $8e osc on m $8d osc off $ce xtal 16m m $cf xtal 32m $c2 normal-speed playback m $c1 double-speed playback $c8 quad-speed playback clv servo system start brake clv muting control 0 db subcode q address conditions address free cont1, cont2 high track jump mode new track count mode old digital attenuator data $00 to $ee osc off xtal 32m playback speed double speed quad speed antishock mode on general-purpose input ports input or output set independently digital filter normal speed on off all pins input off normal speed 16m on data $00 new old low address 1 C stop oscillator
28. other pins; pin 8: tai, pin 12: test1, pin 16: test2, pin 17: test3, pin 26: test4, pin 77: test5, pin 73: testf these are test pins for testing the lsi internal circuits. tai and test1 to test5 have built-in pull-down resistors. 29. ram address control the LC78630E incorporates an 8-bit 2336-word ram on chip. this ram provides an efm demodulated data jitter handling capacity of 8 frames implemented using address control. the LC78630E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the pck side of the clv servo circuit. if the 8 frame buffer capacity is exceeded, the LC78630E forcibly sets the write address to the 0 position. however, since the errors that occur due to this operation cannot be handled with error flag processing, the ic applies muting to the output for a 109 frame period. no. 5121- 28 /33 LC78630E position division ratio or processing C8 or lower forcibly moves to 0 C7 to C1 advancing divisor: 589 0 standard divisor: 588 +1 to +7 fall back divisor: 587 +8 or greater forcibly moves to 0
command table blank entries: unused command items in parentheses as asp commands all commands, except the tj brake ($8c), nothing ($fe), and tchk clear ($ff) are latched. no. 5121- 29 /33 LC78630E $00 (adj. reset) $20 thld period toff low $40 ubit on $60 $01 mute 0 db $21 thld period toff high $41 ubit off $61 $02 $22 new track cnt $42 dout on $62 $03 mute C db $23 old track cnt $43 dout off $63 $04 dm start $24 $44 $64 $05 dm clv $25 $45 $65 $06 dm brake $26 $46 $66 $07 dm stop $27 $47 $67 $08 $28 sto cont $48 ntj cond set $68 $09 address free $29 lch cont $49 pck off $69 $0a $2a rch cont $4a atime priority off $6a $0b $2b $4b atime priority on $6b anti-shock off $0c $2c $4c cont2 rst $6c anti-shock on $0d $2d $4d cont2 set $6d $0e cont1 set $2e $4e $6e df normal speed off $0f tracking off $2f $4f $6f df normal speed on $10 2tj in $30 32tj in $50 $70 $11 1tj in #1 $31 1tj in #3 $51 $71 $12 1tj in #2 $32 $52 1tj in #4 $72 $13 4tj in $33 $53 $73 $14 16tj in $34 $54 $74 $15 64tj in $35 $55 $75 $16 256tchk $36 $56 $76 $17 128tj in $37 $57 $77 ntj in $18 2tj out $38 32tj out $58 $78 $19 1tj out #1 $39 1tj out #3 $59 $79 $1a 1tj out #2 $3a $5a 1tj out #4 $7a $1b 4tj out $3b $5b $7b $1c 16tj out $3c $5c $7c $1d 64tj out $3d $5d $7d $1e $3e $5e $7e $1f 128tj out $3f $5f $7f ntj out
blank entries: unused command items in parentheses as asp commands all commands, except the tj brake ($8c), nothing ($fe), and tchk clear ($ff) are latched. no. 5121- 30 /33 LC78630E $80 $a0 old track jump $c0 $e0 $81 lrch att set $a1 new track jump $c1 double-speed playback $e1 $82 lch att set $a2 $c2 normal-speed playback $e2 $83 rch att set $a3 internal brake cont $c3 $e3 $84 swap off $a4 $c4 internal brake off $e4 $85 swap on $a5 $c5 internal brake on $e5 $86 $a6 $c6 $e6 $87 $a7 $c7 $e7 $88 cdromxa $a8 disk 8 cm set $c8 quad-speed playback $e8 $89 address1 $a9 disk 12 cm set $c9 ck2 polarity inversion $e9 $8a $aa $ca internal brake $ea continuous off $8b cnt1, romxa rst $ab $cb internal brake $eb continuous on $8c tj brake $ac $cc internal brake trkg off $ec $8d osc off $ad $cd internal brake trkg on $ed $8e osc on $ae $ce xtal 16m $ee command noise reduction mode off $8f tracking on $af $cf xtal 32m $ef command noise reduction mode on $90 (f.ofs. adj. st) $b0 no clv phase $d0 $f0 track chk in comparator divisor $91 (f.ofs. adj. off) $b1 clv phase comparator $d1 $f1 divisor: 1/2 $92 (t.ofs. adj. st) $b2 clv phase comparator $d2 $f2 divisor: 1/4 $93 (t.ofs. adj. off) $b3 clv phase comparator $d3 $f3 divisor: 1/8 $94 (lsr. on) $b4 $d4 $f4 $95 (lsr. off/f. sv. on) $b5 $d5 $f5 $96 (lsr. off/f. sv. off) $b6 $d6 $f6 $97 (sp. 8cm) $b7 $d7 $f7 $98 (sp. 12cm) $b8 sled set $d8 variable pitch off $f8 track chk out $99 (sp. off) $b9 $d9 variable pitch on $f9 $9a (sled. on) $ba tes wd wide $da variable pitch set $fa $9b (sled. off) $bb tes wd narw $db port i/o set $fb $9c (ef. bal. st) $bc $dc port output $fc $9d (t. sv. off) $bd $dd port read $fd $9e (t. sv. on) $be $de $fe nothing $9f $bf $df $ff tchk clear
sample application circuit no. 5121- 31 /33 LC78630E
item lc7861ne ? lc7861ke lc78621e lc78622e lc78624e lc 78625 e lc78626e LC78630E m comparison of sanyo cd dsp product functions LC78630E efmpll ram paired with la9210m built-in vco fr = 1.2 k built-in vco fr = 1.2 k built-in vco fr = 1.2 k built-in vco fr = 1.2 k built-in vco fr = 5.1 k built-in vco fr = 1.2 k 16k 16k 2 (4 ) 2 playback speed digital output m m m m m m interpolation 4 4 2 2 4 2 2 zero-cross muting m C12 db, C m C12 db, C m C m C m C12 db, C m C m C bilingual 5 m 2fs 8fs 2 2 5 5 2 5 2 5 5 5 5 5 m 5 5 4.5 to 5.5 v qfp64e 5 5 m 5 5 m m 5 3.6 to 5.5 v qfp80e 5 5 5 5 5 5 m m 3.0 to 5.5 v qfp64e 5 5 5 5 m 5 5 5 3.0 to 5.5 v qfp64e (4) m m 5 5 m m 5 3.0 to 5.5 v qfp80e 1 + (3) 5 unnecessary m 5 5 m m 3.0 to 5.5 v qfp100e 2 + (4) m m 5 5 m m 5 3.6 to 5.5 v qfp80e 5 m m 5 m m m 4fs 5 8fs 4fs 2fs m m m m m general- purpose ports video cd support anti-shock interface anti-shock controller cd text cd-rom interface 1 bit d/a converter low pass filter supply voltage package i/o level meter & peak search 5 m 5 5 m 5 5 digital attenuator 5 m m 5 m m m digital filters digital de-emphasis 2 2 2 2 4 16k 16k 16k 16k 18k output
no. 5121- 33 /33 LC78630E this catalog provide information as of august, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: - not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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